As semiconductor technology has advanced, the amount and speed of logic available on an integrated circuit (IC) has increased more rapidly than the number and performance of input/output (I/O) connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections between them are made by wire bonding at the chip peripheries or by forming high aspect ratio “through die vias” (TDVs). There are several known approaches for stacking ICs. Multiple silicon device layers can be grown epitaxially or fully processed ICs can be bonded for vertical integration.
As ICs have become more complex, employing more and more pins in a limited area, and more I/O signal pins are switching at high speed at the same time, decoupling the power supplies through efficient usage of low inductance capacitors has become increasingly essential. Such capacitors may be integrated into an IC (on-chip) or integrated within the packaging substrate of the IC or the printed circuit board (PCB) to which the IC is mounted (off-chip). The inductance of interconnects connecting the on-chip power supply grid to the off-chip decoupling capacitors is typically too high, reducing the effectiveness of the off-chip decoupling capacitors at high frequencies. Interconnect inductance is even more of a problem for stacked ICs, as the distance between the ICs and the packaging substrate or PCB increases. Thus, it is desirable to integrate decoupling capacitors within close proximity to the on-chip power supply grid.
Conventionally, on-chip capacitors are implemented using polysilicon-over-diffusion and polysilicon-over-polysilicon techniques. Both of these implementations, however, lead to a large area overhead on the layout of the IC. Other on-chip capacitors have been formed by utilizing metal-to-polysilicon or metal-to-metal capacitance. Because the separation between metal layers on the same interconnect plane or neighboring interconnect planes is typically much larger than the gate oxide thickness, the capacitance per unit area is generally smaller. While it is feasible to integrate inter-layer dielectric (ILD) with a higher dielectric constant (high-k), such an ILD leads to higher resistance-capacitance (RC) delay if a signal wire is routed on the metal layer above or below the high-k ILD layer.
Accordingly, there exists a need in the art for an improved method and apparatus for integrated capacitors in stacked ICs.